SIMULATION AND ANALYSIS OF ENCODERS OF INTERFERENCE-RESISTANT CASCADE CODES FOR DYNAMIC SYSTEMS

Authors

DOI:

https://doi.org/10.20998/2079-0023.2023.01.10

Keywords:

immunity, bit, code, code combination, cascade codes, coding, coder, parity check

Abstract

For various channels of information transmission that can be used in local control systems of a wide range of processes, affordable, scalable, and inexpensive transmission methods are needed that allow the necessary information to be transmitted reliably without errors. Errors that occur in discrete, continuous communication channels are the main obstacle to the reliability of transmitted data. The main causes of errors are signal attenuation, noise and various interferences. As a result of the analysis of error statistics in discrete data transmission channels, it was concluded that single and double errors occur in the absolute majority of cases. It is proposed to combat errors by using tamper-resistant coding. Among the interference-resistant codes, redundant block-separated systematic codes are highlighted, among which is the Hamming code. The basis of the interference-resistant coding model is proposed to be the use of a systematic Hamming code followed by cascade coding by adding a parity check bit. The used model made it possible to deal with all the most likely cases of errors. Since this coding model must be flexibly used in different systems, a necessary criterion of the model is its universality. Therefore, the model was tested on a sample with code combinations of different numbers of bits. The purpose of this article is to analyze the dependence of the coding procedure execution time for encoders of different levels: a separate first-stage encoder, as well as a first-stage encoder with the addition of a second-stage encoder. Experiments were conducted with a large sample, which were subsequently analyzed and interpreted. Since the model proved to be flexible, simple, stable and effective as a result of experiments, and the process of combating interference by using cascade codes has proven itself well in world practice, it is recommended for use in various information management systems. The implementation of the coder for interference-resistant data transmission is given.

Author Biographies

Olena Nikulina, National Technical University "Kharkiv Polytechnic Institute"

Doctor of Technical Sciences, Associate Professor, Head of Department Information Systems and Technologies National Technical University «Kharkiv Polytechnic Institute», Kharkiv, Ukraine

Valerii Severyn, National Technical University "Kharkiv Polytechnic Institute"

Doctor of Technical Sciences, Professor, Professor of Department System Analysis and Information-Analytical Technologies National Technical University «Kharkiv Polytechnic Institute», Kharkiv, Ukraine

Vladyslav Sharov, National Technical University "Kharkiv Polytechnic Institute"

Postgraduate of Department Information Systems and Technologies National Technical University «Kharkiv Polytechnic Institute», Kharkiv, Ukraine

References

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Published

2023-07-15

How to Cite

Nikulina, O., Severyn, V., & Sharov, V. (2023). SIMULATION AND ANALYSIS OF ENCODERS OF INTERFERENCE-RESISTANT CASCADE CODES FOR DYNAMIC SYSTEMS. Bulletin of National Technical University "KhPI". Series: System Analysis, Control and Information Technologies, (1 (9), 64–69. https://doi.org/10.20998/2079-0023.2023.01.10

Issue

Section

MATHEMATICAL AND COMPUTER MODELING